(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method for creating a cavity down flip chip package.
(2) Description of the Prior Art
The semiconductor industry is known to be very competitive and is therefore constantly driven to improve semiconductor device performance at competitive prices. The objective of improving device performance can realistically only be achieved by reducing device dimensions, which leads to increased device densities. Devices of increased densities must further be combined to form multi-chip packages that contain not only the high-density semiconductor devices but also contain relatively complex means for the interconnection of the devices that are part of the package.
In many of the complex, multi-device packages a substrate, that is typically ceramic or plastic based, is used for the mounting of devices on the surface thereof and for the formation of the interconnect-interface between the devices and the surrounding circuitry. Many different approaches are used for the purpose of interconnecting multiple semiconductor devices, such as Dual-In-Line packages (DIP""s), Pin Grid Arrays (PGA""s), Plastic Leaded Chip Carriers (PLCC""s) and Quad Flat Packages (QFP""s). Multi layer structures have further been used to connect physically closely spaced integrated circuits with each other. Using this technique, a single substrate serves as an interconnect medium, multiple chips are connected to the interconnect medium forming a device package with high packaging density and dense chip wiring. The chip wiring contains layers of interconnect metal that are interconnected with interconnect vias, layers of dielectric (such as polyimide) or insulating layers separate metal layers that make up the interconnect network and the via and contact points that establish connections between the interconnect networks. The design of overlying and closely spaced interconnect lines are subject to strict rules of design that are aimed at improving package performance despite the high density packaging that is used. For instance, electrical interference between adjacent lines is minimized or avoided by creating interconnect lines for primary signals that intersect under 90 degree angles. Surface planarity must be maintained throughout the construction of multi-layer chip packages due to requirements of photolithography and package reliability. Many of the patterned layers within a layered structure form the base for overlying layers, lack of planarity can therefore have a multiplying effect on overlying layers.
The Quad Flat Package (QFP) has been created to achieve high pin count integrated packages with various pin configurations. The pin I/O connections for these packages are typically established by closely spaced leads distributed along the four edges of the flat package. This limits the I/O count of the packages and therefore the usefulness of the QFP. The Ball Grid Array (BGA) package has been created whereby the I/O connects for the package are distributed around the periphery of the package and over the complete bottom of the package. The BGA package can therefore support more I/O points and provides a more desirable package for high circuit density with high I/O count. The BGA contact points are solder balls that in addition facilitate the process of flow soldering of the package onto a printed circuit board. The solder balls can be mounted in an array configuration and can use 40, 50 and 60 mil spacings in a regular or staggered pattern.
Where circuit density keeps increasing and device feature size continues to be reduced, the effect of the interconnect metal within the package becomes relatively more important to the package performance. Factors that have a negative impact on circuit performance, such as interconnect line resistance, parasitic capacitance, RC-delay constants, crosstalk and contact resistance have a significant impact on the package design and its limitations. A significant power drop may for instance be introduced along the power and ground buses where the reduction of the interconnect metal does not match the reduction in device features. Low resistance metals (such as copper) are therefore finding wider application in the design of dense semiconductor packages.
Increased I/O combined with increased high requirements for high performance IC""s has led to the development of Flip Chip packages. Flip chip technology fabricates bumps (typically Pb/Sn solder) on Al pads and interconnects the bumps directly to the package media, which are usually ceramic or plastic based. The flip-chip is bonded face down to the package through the shortest paths. These technologies can be applied not only to single-chip packaging, but also to higher or integrated levels of packaging in which the packages are larger, and to more sophisticated package media that accommodate several chips to form larger functional units.
The flip-chip technique, using an area array, has the advantage of achieving the highest density of interconnection to the device and a very low inductance interconnection to the package. However, pre-testability, post-bonding visual inspection, and Temperature Coefficient of Expansion (TCE) matching to avoid solder bump fatigue are still challenges. In mounting several packages together, such as surface mounting a ceramic package to a plastic board, the TCE mismatch can cause a large thermal stress on the solder lead joints that can lead to joint breakage caused by solder fatigue from temperature cycling operations.
For devices that have high power dissipation, cavity down BGA packages are frequently used. The BGA cavity down package has a structure such that the semiconductor die and the BGA balls both reside on the bottom side of the BGA substrate, that is the side of the BGA substrate that faces the printed wiring board. The structure thereby allows the top-side of the BGA substrate to be available for heat removal purposes.
As an illustration of a Prior Art cavity down package, a method of packaging a BGA is shown in FIG. 1. The features of this package can be identified as follows:
10xe2x80x2 is the heatsink of the package, heatsink 10xe2x80x2 has a surface that is electrically conductive; mounted in the heatsink is
12xe2x80x2, the semiconductor device; contact points for the die 10xe2x80x2 are closely spaced around the periphery of the die; the chip 12xe2x80x2 is interconnected to surrounding circuitry be means of the interface
14xe2x80x2 which contains one or more layers of interconnect wiring; layer 14xe2x80x2 can contain a stiffener that provides rigidity to the substrate; contact points that have been provided in the surface of chip 12xe2x80x2 are connected to substrate 14xe2x80x2 by means of
16xe2x80x2, the wire bond connections; the wire bond connections provide a wire bonded connection between a contact points on the IC die 12xe2x80x2 and the copper traces 19xe2x80x2 contained in layer
18xe2x80x2, additional points of electrical contact are provided in the surface of substrate 14xe2x80x2 by means of points 18xe2x80x2 which are contact pads to which, typically, contact balls are connected for further mounting of the indicated package; device 12xe2x80x2 is mounted inside a cavity that has been provided in the surface of the heatsink 14xe2x80x2 and contacts the heatsink via
layer 20xe2x80x2, which is a thermally conductive adhesive layer, typically containing epoxy; the device 12xe2x80x2 is further protected from the environment by being encapsulated in layer
22xe2x80x2, which forms an epoxy based protective enclosure for device 12xe2x80x2; the layer
24xe2x80x2 is the adhesive interface between the substrate 14 and the heatsink 10xe2x80x2.
The Prior Art package that is shown in FIG. 1 contains a heat sink in which a cavity is provided for the insertion of a semiconductor die, a substrate that contains one or more layers of interconnect lines and methods of encapsulating the mounted semiconductor die. Other, simpler methods can be used for mounting a semiconductor whereby the die is mounted directly on the surface of a Printed Circuit Board (PCB) while layers of metal interconnect within the PCB are used to provide the I/O connections of the mounted die to surrounding circuitry. In most applications of this kind, the die is still provided with contact balls, these contact balls rest directly on the surface of the PCB and are connected to electrical points of contact that are opened in the surface of the PCB.
U.S. Pat. No. 5,583,378 (Marrs et al.) (cited by the inventor) shows a metal panel 204 used as a thermal conductor. The chip 202 is attached to the thermal conductor 204 by metal epoxies 206. See FIG. 2A, also see FIGS. 4A through 4L.
U.S. Pat. No. 5,777,386 (Higashi et al.) (cited by the inventor) shows a flip chip package having a heat conductor but ceramic substrate. See col. 3, line 65. The package has heat conducting pattern 12 that conducts heat to the substrate (e.g. PCB) by solder balls.
U.S. Pat. No. 5,874,321 (Templeton, Jr. et al.) teaches a cavity up package with a conductive lid.
U.S. Pat. No. 6,020,637 (Karnezos) shows a heat spreader for a package.
U.S. Pat. No. 5,578,869 (Hoffman et al.) shows a metal base/panel for a package.
U.S. Pat. No. 5,289,337 (aghazadeh et al.) shows a related package.
A principle objective of the invention is to provide a method for the fabrication of high-density substrates that is used for the packaging of cavity-down flip chip semiconductor devices.
The process of the invention starts with a metal panel, overlying the metal panel is created an interconnect substrate making use of BUM and thin film processing technology while the process of the invention enables the use of stacked vias for the A connection of the flip chip bumps. The process of the invention creates, for instance, two patterned layers on the surface of the metal panel whereby the metal panel is used as the ground terminal of the power supply. The first layer that is created on the surface of the metal panel can be the power supply layer (this layer can also be used for some fan-out interconnect lines), selected points within the first layer are in direct contact with the metal panel for purposes of improved heat exchange to the metal panel and of improved ground power supply. The second layer that is created on the surface of the metal panel is primarily used for (fan-out) interconnect lines. The flip chip bumps are, under the process of the invention, connected to the second layer of the interconnect substrate. The process of the invention does not require any additional structures such as a dam for the containment of insulating encapsulation material (underfill) that at times is provided around a perimeter of a well into which a flip chip is inserted, making the process of the invention most cost effective.